The present invention relates to the field of microelectronic integrated circuits. Specifically, the present invention relates to a memory device including a homogeneous oxynitride tunneling dielectric layer.
A flash or block erase memory (flash memory), such as, Electrically Erasable Programmable Read-Only Memory (Flash EEPROM), includes an array of cells which can be independently programmed and read. The size of each cell and thereby the memory as a whole are made smaller by eliminating the independent nature of each of the cells. As such, all of the cells are erased together as a block.
A memory of this type includes individual Metal-Oxide Semiconductor (MOS) memory cells that are field effect transistors (FETs). Each FET, or flash, memory cell includes a source, drain, floating gate and control gate to which various voltages are applied to program the cell with a binary 1 or 0, or erase all of the cells as a block. The flash memory cell provides for nonvolatile data storage.
A typical configuration of a flash memory cell 100 consists of a thin, high-quality tunnel oxide layer 140 sandwiched between a conducting polysilicon floating gate and a crystalline silicon semiconductor substrate. The tunnel oxide layer is typically composed of silicon oxide (SixOy). The substrate includes a source region and a drain region that can be separated by an underlying channel region. A control gate is provided adjacent to the floating gate, and is separated by an interpoly dielectric. Typically, the interpoly dielectric can be composed of an oxide-nitride-oxide (ONO) structure.
The flash memory cell stores data by holding charge within the floating gate. In a write operation, charge can be placed on the floating gate through hot electron injection, or Fowler-Nordheim (F-N) tunneling. In addition, F-N tunneling can be typically used for erasing the flash memory cell through the removal of charge on the floating gate.
A common failure in flash memory is a programming failure due to an over-erased cell. During an erase process, not all bits in an array erase in the same way. FIG. 1 is a chart 100 illustrating a Gaussian distribution (illustrated by curve 140) of threshold voltages for an array of flash memories that have been erased. Line 110 represents the reference voltage, and its corresponding current, from which it is determined whether a memory cell has been erased. Threshold voltages of memory cells below the reference voltage indicate that those memory cells are erased.
When a column of flash memory cells, in an array of flash memory cells, is erased in parallel, some memory cells are erased very quickly (fast bits) while other memory cells are harder to erase (slow bits). A small percentage of over-erased bits having threshold voltages below 0 volts is shown in tail region 120 of FIG. 1.
In addition, the fast bits create a non-Gaussian distribution of threshold voltages as indicated by dotted line 130, which leads to a wider distribution of threshold voltages. This can be problematic especially when implementing multi-level voltage devices, where voltage tolerances are reduced.
Unfortunately, having an over-erased cell on the same column line with a programmed bit can cause a failure when the programmed bit is read. The over-erased cell produces a leakage current and causes the entire column to malfunction. In particular, the current that is read from the column should be below the reference current (IRef) that corresponds to the threshold voltage illustrated by line 110, when reading a programmed cell having a higher threshold voltage. IRef is the erased cell reference current used for comparison.
However, if an over-erased cell is in the same column as that of the programmed cell, the over-erased cell has a threshold voltage that is less than 0 producing a leakage current (ILeak). As such, the total current read from the column will include the current from the programmed memory cell (IProgram) and the leakage current. If the sum of IProgram +ILeakage  greater than IRef, then the total current being read from the column is greater than the reference current, and the programmed cell appears to be erased.
One prior art solution is to slightly program the over-erased cells from the drain side to bring the threshold voltages of the over-erased cells in tail region 120 back above 0 volts. The prior art process is named Automatic Program Disturb after Erase (APDE). The APDE process includes applying approximately 5 Volts to the drain region of a memory cell, and grounding the control gate and source regions. The respective voltages are applied for approximately 100 ms in order to weakly reprogram the over-erased cell to approximately 0 volts.
Unfortunately, the APDE process is a column by column fix, which can become an inefficient and lengthy process, especially as memory arrays become larger. For example, the APDE process is applied to memory cells in an entire column in parallel. Only the bits that are over-erased will program. The memory cells that are not over-erased will not program.
Additionally, the APDE process will not correct memory cells that have larger negative threshold voltages. In other words, the APDE process can only correct threshold voltages up to a limit. Line 160 illustrates the negative threshold voltage beyond which the APDE process is unable to reprogram threshold voltages back to approximately 0 Volts. As such, the APDE process cannot correct memory cells within tail region 120 with highly negative threshold voltages that extend the distribution 100 well into the negative region.
The present invention provides a method for repairing over-erasure of floating gate memory devices that is applied on an array-wide basis for better efficiency. Embodiments of the present invention also provide for a method for compacting the distribution of threshold voltages for memory cells in an array of memory cells
Specifically, one embodiment of the present invention discloses a method for performing a program disturb operation for repairing over-erasure of non-volatile memory. The non-volatile memory comprises at least one array of memory cells arranged in a plurality of rows and a plurality of columns, a plurality of word lines coupled to said plurality of rows, a plurality of bit lines coupled to said plurality of columns. Each of the memory cells comprise a source, a control gate coupled to a respective word line, and a drain coupled to a respective bit line, and is capable of storing a respective bit.
The method for correcting over-erasure of the array of memory cells comprises the step of performing an array wide program disturb operation for repairing over-erasure of fast bits. The program disturb operation is applied simultaneously to the entire array making it compatible with channel erase schemes. The fast bits are programmed back to a normal state to approximately 0 Volts by applying a substrate voltage to a substrate common to the array of memory cells. A gate voltage is applied to a plurality of word lines coupled to control gates of the array of memory cells. A program pulse time for applying voltages ranges from approximately 10 microseconds to 1 second. A voltage differential between a control gate and the substrate in a memory cell of the array is in the range of approximately 9 Volts to about 20 Volts.
In another embodiment, the method described above for performing an array wide program disturb operation compacts the distribution of voltage thresholds for memory cells in the array of non-volatile memory cells. The distribution of voltage thresholds is tighter than a Gaussian distribution of voltage thresholds for memory cells after an erase operation.